The present invention relates to an image pickup device for converting incident light into an electric signal, particularly to an amplifying solid-state image pickup device (particularly, MOS amplifying solid-state image pickup device) and its operating method.
FIG. 1 is a circuit diagram of an amplifying solid-state image pickup device referred to as a general amplifying MOS sensor.
In FIG. 1, unit cells are two-dimensionally arranged which comprise photodiodes 1.sub.11, 1.sub.12, . . . , 1.sub.21, 1.sub.22, . . . for performing photoelectric conversion, amplifying transistors 2.sub.11, 2.sub.12, . . . , 2.sub.21, 2.sub.22, . . . for amplifying signals of the photodiodes 1.sub.11, 1.sub.12, . . . , 1.sub.21, 1.sub.22, . . . , vertical select transistors 3.sub.11, 3.sub.12, . . . , 3.sub.21, 3.sub.22, . . . for selecting a line for reading a signal, reset transistors 4.sub.11, 4.sub.12, . . . , 4.sub.21, 4.sub.22, . . . for resetting a signal charge, and signal charge transfer transistors 5.sub.11, 5.sub.12, . . . , 5.sub.21, 5.sub.22, . . . for transferring the charges of the photodiodes 1.sub.11, 1.sub.12, . . . , 1.sub.21, 1.sub.22, . . . to gate regions of the amplifying transistors 2.sub.11, 2.sub.12, . . . , 2.sub.21, 2.sub.22, . . . . Though FIG. 1 shows a case in which 2.times.2 unit cells are arranged, more than 2.times.2 unit cells are actually arranged.
Horizontal address lines 7.sub.1, 7.sub.2, . . . and charge transfer control lines 8.sub.1, 8.sub.2, . . . , and reset lines 9.sub.1, 9.sub.2, . . . are extended to a horizontal direction from a vertical shift register 6 and are respectively connected to each of the unit cells. That is, the horizontal address lines 7.sub.1, 7.sub.2, . . . are connected to gates of the vertical select transistors 3.sub.11, 3.sub.12, . . . , 3.sub.21, 3.sub.22, . . . to determine a line for reading a signal. The charge transfer control lines 8.sub.1, 8.sub.2, . . . are connected to gates of the signal charge transfer transistors 5.sub.11, 5.sub.12, . . . , 5.sub.21, 5.sub.22, . . . . Moreover, the reset lines 9.sub.1, 9.sub.2, . . . are connected to gates of the reset transistors 4.sub.11, 4.sub.12, . . . , 4.sub.21, 4.sub.22, . . .
Sources of the amplifying transistors 2.sub.11, 2.sub.12, . . . , 2.sub.21, 2.sub.22, . . . are connected to vertical signal lines 10.sub.1, 10.sub.2, . . . Load transistors 13.sub.1, 13.sub.2, . . . connected to a common gate line 11 and a common source line 12 are provided for one ends of the vertical signal lines 10.sub.1, 10.sub.2, . . . Moreover, the horizontal select transistors 15.sub.1, 15.sub.2 . . . through the vertical signal lines 5.sub.11, 5.sub.12, . . . are connected to the other ends of the vertical signal lines 10.sub.1, 10.sub.2, . . . through noise suppression circuits 141, 14.sub.2, . . . The horizontal select transistors 15.sub.1, 15.sub.2, . . . are selected by a selection pulse supplied from a horizontal shift register 16 and connected to a horizontal signal line 17.
The noise suppression circuits 14.sub.1, 14.sub.2, . . . are circuits for detecting the difference between cases in which a signal is present and absent in the vertical lines 10.sub.1, 10.sub.2, . . . . FIG. 2 is a circuit diagram showing an example of a structure of the noise suppression circuits.
In FIG. 2, the vertical signal line 10 is connected to the gate of a slice transistor 19. A slice capacitor 20 and a slice capacitor reset transistor 21 are connected to the source of the slice transistor 19 and a slice charge storage capacitor 21 and a slice charge storage capacitor reset transistor 22 are connected to the drain of the slice transistor 19 as illustrated. Moreover, FIG. 2 shows a slice-capacitor reset transistor common source line 24, slice capacitor reset transistor common gate 25, a slice-capacitor control line 26, a DC line 27, and a slice-charge storage capacitor reset transistor common gate 28.
FIG. 3 is a timing chart for explaining operations of a conventional device.
A BL pulse shows a period I for suppressing noises of a noise suppression circuit 14 and a period II for reading signals of the photodiodes 1 to the horizontal signal line 17.
First, the period I is described below. When an address pulse S1.sub.1 which makes the horizontal address line 7.sub.1 high-level is applied, only a transistor for selecting the line is turned on, a source follower circuit is constituted with the amplifying transistors 2.sub.11 and 2.sub.12 and the load transistors 13.sub.1 and 13.sub.2 in this row, and a voltage almost equal to the gate voltage of the amplifying transistors 2.sub.11 and 2.sub.12 appears on the vertical signal lines 10.sub.1 and 10.sub.2.
Moreover, a reset pulse S2.sub.1 is generated in a reset line 8.sub.1 and a reset transistor 4.sub.1 is turned on, and thereby a voltage when there is no signal is generated in the gate of the amplifying transistor 2.sub.11. In this case, only a noise voltage when there is no signal is generated in the vertical signal lines 10.sub.1 and 10.sub.2. That is, only noises are applied to the gate of the slice transistor 19.
A slice capacitor reset pulse S3.sub.1 is applied to a slice-capacitor reset transistor common gate 25 and the slice capacitor 20 is preset.
Then, a first slice pulse S4.sub.1 is applied to the slice capacitor control line 26 connected to the slice capacitor 20 and some of the charges stored in the slice capacitor 20 are transferred to the drain of the slice transistor 19 through the gate channel of the transistor 19. Charges corresponding to the noise voltage applied to the gate of the slice transistor 19 are left in the slice capacitor 20.
The charges transferred from the drain of the slice transistor 19 and entering the slice charge storage capacitor 22 also have a quantity related to noise charges. However, a first slice-charge storage capacitor reset pulse S5.sub.1 is applied to the slice-charge storage capacitor reset transistor common gate 28 and the slice charge stored capacity is reset.
Moreover, a second slice pulse S6.sub.1 and a second slice charge storage capacitor reset pulse S7.sub.1 are applied to accurately keep a noise applied state.
Then, a signal charge transfer pulse S8.sub.1 is applied to the charge transfer control line 9.sub.1, the signal charge transfer transistor 5.sub.11 is turned on, and signal charges are transferred to the gate region of the amplifying transistor 2.sub.11. A signal voltage appears on the vertical signal lines 10.sub.1 and 10.sub.2 and it is applied to the gate of the slice transistor 19.
Then, a third slice pulse S9.sub.1 is applied and some of the charges stored in the slice capacitor 20 pass through the gate channel of the slice transistor 19 and are transferred to the slice charge storage capacitor 22. Because the charges corresponding to noises is stored in the slice capacitor 20 and a signal voltage on which noises are superimposed is applied to the gate of the slice transistor 19, only charges corresponding to the signal from which noise components are deducted are transferred to the slice charge storage capacitor 22. Accordingly, only signal charges without noise are stored in the slice charge capacitor.
Then, in the period II, horizontal select pulses S10.sub.11 and S10.sub.12 are respectively applied to the gates of the horizontal select transistors 15.sub.1 and 15.sub.2 and signal charges in the slice charge storage capacitor 22 are read out to the horizontal signal line 17. Read signals S11.sub.11 and S11.sub.12 respectively correspond to signals of the photodiodes 1.sub.11 and 1.sub.12.
It is possible to read signals from the subsequent rows similarly to the case.
As described above, even a type of MOS image pickup device including an amplifying transistor in the unit pixel has sensitivity lower than that of an image pickup device having a CCD. This is because the performance of an amplifying transistor present in the unit pixel of an amplifying MOS image pickup device is almost the same as the performance of a transistor of an output amplifier present at the final stage of CCD image pickup devices when the fabrication processes of the both transistors are the same.
A CCD image pickup device is a device hardly having noises and therefore, it is estimated that noises are generated by only an output amplifier. In the case of an amplifying MOS image pickup device, however, even after amplification is performed by the unit pixel, new noises are superimposed in several transistors because signals pass through the transistors until they are output to an output terminal.
FIG. 4 shows a example of a conventional amplifier used for an amplifying solid-state image pickup device, which was proposed by T. Ozaki et al. in 1991 (T. Ozaki, H. Kinugusa, and T. Nishida, "A low-Noise Line-Amplified MOS image pickup devices", IEEE Trans. Electron Devices, Vol. 38, no. 8, pp. 969-975, May 1991").
In the case of a conventional solid-state image pickup device, the amplifier in the document is connected to each signal line or pixel to amplify a pixel signal. In the case of this circuit, the output of an amplifier 53 is connected with an input terminal through a capacitance 52 connected with an amplifier in parallel and a gate switch 54 is connected with an input through a bias capacitance (coupling capacitance) 50. Thereby, as shown in FIG. 5, an operating point is shifted along the curve to increase the dynamic range of output. In the case of this circuit, an operating point 67 moves (AUTO ZERO BIASING) so that V.sub.IN becomes equal to V.sub.OUT when the switch 54 is turned on and the charged stored in the capacitance 50 are read to and amplified by an amplifier. Thereafter, the switch 54 is turned on again and the amplifier is reset. This circuit sets the amplifier to a high gain and controls the gain by the capacitance 52 connected with the amplifier in parallel.
FIG. 6 shows a variable gain amplifier based on a general differential amplifier. This circuit makes it possible to control a gain by adjusting the resistance value R.sub.0 of a resistance and the gain is shown by the following expression. EQU G=(R.sub.2 /2R.sub.2)(1+R.sub.2 /2R.sub.0)(e1-e2)
When utilizing the circuit in FIG. 6 by using a differential amplifier constituted with a MOS transistor, a variable gain control circuit using a MOS transistor is obtained. However, this structure becomes complex and the resistance in FIG. 6 prevents the power consumption from reduction. Moreover, because the number of component transistors increases, a simpler circuit is desired.
As described above, a conventional variable gain amplifier used for a MOS amplifying solid-state image pickup device has a complex structure and problems of noises due to a threshold deviation of a transistor and coupling of signal line capacitance and easily causes fluctuation in gains and signal noises.